NXP Semiconductors /MIMXRT1011 /ADC_ETC /TRIG3_CHAIN_1_0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TRIG3_CHAIN_1_0

Description

ETC_TRIG Chain 0/1 Register

Fields

CSEL0	CHAIN0 CSEL ADC channel selection
HWTS0	CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
B2B0	CHAIN0 B2B 1’b0: Disable B2B, wait until interval is reached 1’b1: Enable B2B, back to back ADC trigger
IE0	CHAIN0 IE 2’b00: Finished Interrupt on Done0 2’b01: Finished Interrupt on Done1 2’b10: Finished Interrupt on Done2 2’b11: Finished Interrupt on Done3
IE0_EN	IRQ enable
CSEL1	CHAIN1 CSEL ADC channel selection
HWTS1	CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
B2B1	CHAIN1 B2B 1’b0: Disable B2B, wait until interval is reached 1’b1: Enable B2B, back to back ADC trigger
IE1	CHAIN1 IE 2’b00: Finished Interrupt on Done0 2’b01: Finished Interrupt on Done1 2’b10: Finished Interrupt on Done2 2’b11: Finished Interrupt on Done3
IE1_EN	IRQ enable

Links

() ()